MEMORY HIERARCHY DESIGN FOR CHIP MULTIPROCESSORS
A Compiler Directed Approach
978-3-639-11515-4
3639115155
156
2008-12-23
59.00 €
eng
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This book presents memory hierarchy design and data
access management methodology. First, memory
hierarchy design and data allocation problem is
discussed, followed by a compiler-driven approach to
data compression for reducing memory space
occupancy. Third, compiler supported loop-data
optimization problem to improve locality of data
accesses for a given application code is discussed.
Since parallelization is a key concept in achieving
the best performance, a constraint network based
formulation has been discussed in the fourth
chapter. In the last part, book discusses advanced
techniques such as the memory optimization in a 3D
architecture to minimize data access costs under
temperature.
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